1. Field of the Invention
The present invention relates to an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device and more particularly to an array substrate for an IPS mode LCD device having a repair pattern and a method of fabrication the array substrate.
2. Discussion of the Related Art
A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and the TFT, and the color filter substrate may include a color filter layer and a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode. However, since the AM-LCD device uses a vertical electric field, the AM-LCD device has a bad viewing angle.
An IPS mode LCD device may be used to resolve the above-mentioned limitations. FIG. 1 is a cross-sectional view of an IPS mode LCD device according to the related art. As shown in FIG. 1, the array substrate and the color filter substrate are separated and face each other. The array substrate includes a first substrate 10, a common electrode 17 and a pixel electrode 30. Though not shown, the array substrate may include a TFT, a gate line and a data line. The color filter substrate includes a second substrate 9, a color filter layer (not shown), and so on. A liquid crystal layer 11 is interposed between the first substrate 10 and the second substrate 9. Since the common electrode 17 and the pixel electrode 30 are formed on the first substrate 10 on the same level, a horizontal electric field “L” is generated between the common and pixel electrodes 17 and 30.
FIGS. 2A and 2B are cross-sectional views showing turned on/off conditions of an IPS mode LCD device according to the related art. As shown in FIG. 2A, when the voltage is applied to the IPS mode LCD device, liquid crystal molecules 11a above the common electrode 17 and the pixel electrode 30 are unchanged. But, liquid crystal molecules 11b between the common electrode 17 and the pixel electrode 30 are horizontally arranged due to the horizontal electric field “L”. Since the liquid crystal molecules are arranged by the horizontal electric field, the IPS mode LCD device has a characteristic of a wide viewing angle. FIG. 2B shows a condition when the voltage is not applied to the IPS mode LCD device. Because an electric field is not generated between the common and pixel electrodes 17 and 30, the arrangement of liquid crystal molecules 11 is not changed.
FIG. 3 is a plane view showing an array substrate for an IPS mode LCD device according to the related art. As shown in FIG. 3, a gate line 43, a common line 47 and a data line 60 are formed on a first substrate 40. The common line 47 is parallel to and spaced apart from the gate line 43. The data line 60 crosses the gate line 43 to define a pixel region P.
A TFT Tr including a gate electrode 45, a semiconductor layer (not shown), a source electrode 53 and a drain electrode 55 is formed at crossing of the gate and data lines 43 and 60. The gate electrode 45 is connected to the gate line 43. The gate electrode 45 may be a portion of the gate line 43. The source electrode 53 is connected to the data line 60 and spaced apart from the drain electrode 55. In addition, a plurality of pixel electrodes 70a and 70b and a plurality of common electrodes 49a and 49b are formed in the pixel region P. The plurality of pixel electrodes 70a and 70b and the plurality of common electrodes 49a and 49b are parallel to and alternately arranged with each other. The plurality of pixel electrodes 70a and 70b are connected to the drain electrode 55 through a drain contact hole 67. The plurality of common electrodes 49a and 49b are connected to the common line 47. The plurality of common electrodes 49a and 49b may extend from the common line 47.
As mentioned above, the IPS mode LCD device of FIG. 3 has a wide viewing angle due to a horizontal electric field between the common and pixel electrodes. However, there are some limitations. Particularly, when an electric line, e.g., the data line, is disconnected during a fabricating process, it is difficult to repair the disconnected data line and thus, the production yield is reduced. Moreover, although not shown in FIG. 3, since a gate insulating layer and a passivation layer are interposed between the common electrode and the pixel electrode, an electric field between the common electrode and the pixel electrode is not perfectly horizontal such that a liquid crystal layer is driven with unexpected arrangement. Furthermore, since a magnitude of the electric field between the common electrode and the pixel electrode decreases due to the gate insulating layer and the passivation layer, power consumption increases.